1. Field of the Invention
The present invention relates generally to a synchronous detector, and is directed more particularly to a synchronous detector adapted to detect an information signal modulated on a carrier which is simple in construction and improved in operating characteristics.
2. Description of the Prior Art
In general, as a video detector system of a television receiver, there has been proposed a so-called synchronous detecting system in which an IF (intermediate frequency) carrier signal extracted from a VIF (video intermediate frequency) signal is used to directly switch the VIF signal.
A prior art synchronous detector circuit will be now described with reference to FIG. 1. In the example of FIG. 1, the signal from an antenna 1 is fed to a tuning circuit 2 in which a VIF signal is derived from a desired broadcast wave. This VIF signal is fed through a band pass filter 3 to a VIF signal amplifier 4, and the output therefrom is fed to a multiplier circuit 5 which forms the synchronous detector circuit. The output from the amplifier 4 is also supplied to a band pass filter 6 with a frequency of 58.75 MHz, for example, for extracting the video intermediate carrier wave. The signal from the band pass filter 6 is applied through a limiter circuit 7 to the multiplier circuit 5. The synchronously detected video signal from the multiplier circuit 5 is delivered to an output terminal 8.
A video intermediate frequency carrier extracting circuit, which is made by combining the band pass filter 6 and the limiter circuit 7, may be as shown in FIG. 2. In the example of FIG. 2, the output terminals of the amplifier 4, from which VIF signals opposite in phase are derived, are respectively connected to the bases of NPN transistors 11a and 11b connected differentially. The emitters of the transistors 11a and 11b are connected together to ground through a constant current source 12. The limiter circuit 7, which consists of diodes 13a and 13b connected in opposite directions, and the band pass filter 6, which is formed of a capacitor 14 and a coil 15 in parallel, are connected between the collectors of the transistors 11a and 11b. The collectors thereof are also connected through respective resistors 16a and 16b to a power source terminal 17. Accordingly, the carrier of the VIF signal can be extracted across the collectors of the transistors 11a and 11b.
The carrier thus extracted from the collectors of the transistors 11a and 11b is supplied through transistors 21a and 21b, each being in an emitter follower configuration, to the bases of two sets of transistor differential circuits 22a and 22b which form the multiplier circuit 5. The connection points between the emitters of the two sets of transistor differential circuits 22a and 22b are respectively grounded through a transistor 23a and a constant current source 24, and through a transistor 23b and a constant current source 24b. The emitters of the transistors 23a and 23b are connected to each other through a resistor 25, and the VIF signals opposite in phase from the amplifier 4 are fed to the bases of the transistors 23a and 23b. In FIG. 2, reference numeral 26 represents the power source terminal for this circuit.
According to the circuit shown in FIG. 2, the synchronously detected video signals are derived at the collectors of the transistor differential circuits 22a and 22b and then delivered to output terminals 8a and 8b.
In the circuit of FIG. 2, since the diodes 13a and 13b, forming the limiter circuit 7, are connected in parallel with the bandpass filter 6, the Q of the bandpass filter 6 is lowered and hence the extracted carrier is deteriorated in purity. As a result, the interference characteristics (cross-color, 920 KH.sub.z beat and so on) upon the synchronous detection is deteriorated.
FIG. 3 shows a circuit which was previously proposed by the applicant same as that of this application so as to avoid the above defect. In this circuit, the output terminals of the amplifier 4 are respectively connected through resistors 31a and 31b to the bases of emitter follower transistors 32a and 32b, and the bandpass filter 6 is connected between the bases of the transistors 32a and 32b. The collectors thereof are connected together to the power source terminal 26. The emitters of transistors 32a and 32b are respectively grounded through constant current sources 34a and 34b and also connected to the bases of transistors 35a and 35b which are connected differentially to form a limiter amplifier. The transistors 35a and 35b have the emitters connected together to the ground through a constant current source 36 and the collectors connected together through resistors 37a and 37b to a power source terminal 38. With the circuit of FIG. 3, the carrier of the VIF signal are extracted across the collectors of the transistors 35a and 35b.
According to the previously proposed circuit shown in FIG. 3, since one band pass filter 6 is connected through the emitter follower transistors 32a and 32b to the transistors 35a and 35b forming the limiter amplifier, the Q of the band pass filter 6 can be made high and hence the carrier high in purity can be extracted.
With the circuit of FIG. 3, however, there is generated bad influence on the bases of transistors 35a and 35b by the mirror capacity and hence the phase characteristic of the output signal is deteriorated.
In detail, since there exists the collector-base capacity in each of the transistors 35a and 35b, a model shown in FIG. 4 is considered and then an input impedance Zin is calculated.
From FIG. 4, the following expressions (1) to (3) are derived. ##EQU1## where G.sub.v is the voltage gain of the transistor.
From the equafollowing equation (4) is derived. EQU v.sub.i -(G.sub.v .multidot.v.sub.i +i.sub.f .multidot.Z.sub.L)=i.sub.f .multidot.Z.sub.f .thrfore.(1-G.sub.v)v.sub.i =i.sub.f (Z.sub.L +Z.sub.f) (4)
Since the following equation (5) is taken to be established, EQU i.sub.i =i.sub.b +i.sub.f ( 5)
the following equation (6) is obtained by substituting the equations (1) and (4) to the equation (5) ##EQU2##
From the above equation (6), the input impedance Zin can be expressed as follows: ##EQU3##
If it is assumed that h.sub.fe .multidot.Z.sub.E =.infin., the input inpedance Zin is expressed as follows: ##EQU4##
Further, if it is assumed that Z.sub.f =1/(j.omega.C), the input impedance Zin is expressed as follows: ##EQU5##
In this case, the value of G.sub.v .multidot.C is the mirror capacity, and the mirror capacity varies dependent on the voltage gain G.sub.v while G.sub.v varies dependent on the level of the input signal. Therefore, the mirror capacity is varied in response to the level of the input signal. Due to the variation of the mirror capacity, the phase of the output signal is varied and hence the phase characteristic of the circuit is deteriorated.